mirror of https://github.com/axmolengine/axmol.git
281 lines
7.3 KiB
C
281 lines
7.3 KiB
C
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/*
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** Definitions for PPC CPUs.
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** Copyright (C) 2005-2013 Mike Pall. See Copyright Notice in luajit.h
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*/
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#ifndef _LJ_TARGET_PPC_H
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#define _LJ_TARGET_PPC_H
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/* -- Registers IDs ------------------------------------------------------- */
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#define GPRDEF(_) \
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_(R0) _(SP) _(SYS1) _(R3) _(R4) _(R5) _(R6) _(R7) \
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_(R8) _(R9) _(R10) _(R11) _(R12) _(SYS2) _(R14) _(R15) \
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_(R16) _(R17) _(R18) _(R19) _(R20) _(R21) _(R22) _(R23) \
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_(R24) _(R25) _(R26) _(R27) _(R28) _(R29) _(R30) _(R31)
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#define FPRDEF(_) \
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_(F0) _(F1) _(F2) _(F3) _(F4) _(F5) _(F6) _(F7) \
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_(F8) _(F9) _(F10) _(F11) _(F12) _(F13) _(F14) _(F15) \
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_(F16) _(F17) _(F18) _(F19) _(F20) _(F21) _(F22) _(F23) \
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_(F24) _(F25) _(F26) _(F27) _(F28) _(F29) _(F30) _(F31)
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#define VRIDDEF(_)
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#define RIDENUM(name) RID_##name,
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enum {
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GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
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FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
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RID_MAX,
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RID_TMP = RID_R0,
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/* Calling conventions. */
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RID_RET = RID_R3,
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RID_RETHI = RID_R3,
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RID_RETLO = RID_R4,
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RID_FPRET = RID_F1,
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/* These definitions must match with the *.dasc file(s): */
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RID_BASE = RID_R14, /* Interpreter BASE. */
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RID_LPC = RID_R16, /* Interpreter PC. */
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RID_DISPATCH = RID_R17, /* Interpreter DISPATCH table. */
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RID_LREG = RID_R18, /* Interpreter L. */
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RID_JGL = RID_R31, /* On-trace: global_State + 32768. */
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/* Register ranges [min, max) and number of registers. */
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RID_MIN_GPR = RID_R0,
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RID_MAX_GPR = RID_R31+1,
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RID_MIN_FPR = RID_F0,
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RID_MAX_FPR = RID_F31+1,
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RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
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RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR
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};
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#define RID_NUM_KREF RID_NUM_GPR
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#define RID_MIN_KREF RID_R0
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/* -- Register sets ------------------------------------------------------- */
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/* Make use of all registers, except TMP, SP, SYS1, SYS2 and JGL. */
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#define RSET_FIXED \
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(RID2RSET(RID_TMP)|RID2RSET(RID_SP)|RID2RSET(RID_SYS1)|\
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RID2RSET(RID_SYS2)|RID2RSET(RID_JGL))
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#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED)
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#define RSET_FPR RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR)
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#define RSET_ALL (RSET_GPR|RSET_FPR)
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#define RSET_INIT RSET_ALL
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#define RSET_SCRATCH_GPR (RSET_RANGE(RID_R3, RID_R12+1))
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#define RSET_SCRATCH_FPR (RSET_RANGE(RID_F0, RID_F13+1))
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#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
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#define REGARG_FIRSTGPR RID_R3
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#define REGARG_LASTGPR RID_R10
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#define REGARG_NUMGPR 8
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#define REGARG_FIRSTFPR RID_F1
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#define REGARG_LASTFPR RID_F8
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#define REGARG_NUMFPR 8
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/* -- Spill slots --------------------------------------------------------- */
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/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
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**
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** SPS_FIXED: Available fixed spill slots in interpreter frame.
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** This definition must match with the *.dasc file(s).
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**
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** SPS_FIRST: First spill slot for general use.
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** [sp+12] tmplo word \
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** [sp+ 8] tmphi word / tmp dword, parameter area for callee
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** [sp+ 4] tmpw, LR of callee
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** [sp+ 0] stack chain
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*/
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#define SPS_FIXED 7
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#define SPS_FIRST 4
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/* Stack offsets for temporary slots. Used for FP<->int conversions etc. */
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#define SPOFS_TMPW 4
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#define SPOFS_TMP 8
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#define SPOFS_TMPHI 8
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#define SPOFS_TMPLO 12
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#define sps_scale(slot) (4 * (int32_t)(slot))
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#define sps_align(slot) (((slot) - SPS_FIXED + 3) & ~3)
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/* -- Exit state ---------------------------------------------------------- */
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/* This definition must match with the *.dasc file(s). */
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typedef struct {
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lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
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int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
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int32_t spill[256]; /* Spill slots. */
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} ExitState;
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/* Highest exit + 1 indicates stack check. */
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#define EXITSTATE_CHECKEXIT 1
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/* Return the address of a per-trace exit stub. */
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static LJ_AINLINE uint32_t *exitstub_trace_addr_(uint32_t *p, uint32_t exitno)
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{
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while (*p == 0x60000000) p++; /* Skip PPCI_NOP. */
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return p + 3 + exitno;
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}
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/* Avoid dependence on lj_jit.h if only including lj_target.h. */
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#define exitstub_trace_addr(T, exitno) \
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exitstub_trace_addr_((MCode *)((char *)(T)->mcode + (T)->szmcode), (exitno))
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/* -- Instructions -------------------------------------------------------- */
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/* Instruction fields. */
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#define PPCF_CC(cc) ((((cc) & 3) << 16) | (((cc) & 4) << 22))
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#define PPCF_T(r) ((r) << 21)
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#define PPCF_A(r) ((r) << 16)
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#define PPCF_B(r) ((r) << 11)
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#define PPCF_C(r) ((r) << 6)
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#define PPCF_MB(n) ((n) << 6)
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#define PPCF_ME(n) ((n) << 1)
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#define PPCF_Y 0x00200000
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#define PPCF_DOT 0x00000001
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typedef enum PPCIns {
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/* Integer instructions. */
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PPCI_MR = 0x7c000378,
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PPCI_NOP = 0x60000000,
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PPCI_LI = 0x38000000,
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PPCI_LIS = 0x3c000000,
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PPCI_ADD = 0x7c000214,
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PPCI_ADDC = 0x7c000014,
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PPCI_ADDO = 0x7c000614,
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PPCI_ADDE = 0x7c000114,
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PPCI_ADDZE = 0x7c000194,
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PPCI_ADDME = 0x7c0001d4,
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PPCI_ADDI = 0x38000000,
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PPCI_ADDIS = 0x3c000000,
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PPCI_ADDIC = 0x30000000,
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PPCI_ADDICDOT = 0x34000000,
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PPCI_SUBF = 0x7c000050,
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PPCI_SUBFC = 0x7c000010,
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PPCI_SUBFO = 0x7c000450,
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PPCI_SUBFE = 0x7c000110,
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PPCI_SUBFZE = 0x7c000190,
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PPCI_SUBFME = 0x7c0001d0,
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PPCI_SUBFIC = 0x20000000,
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PPCI_NEG = 0x7c0000d0,
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PPCI_AND = 0x7c000038,
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PPCI_ANDC = 0x7c000078,
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PPCI_NAND = 0x7c0003b8,
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PPCI_ANDIDOT = 0x70000000,
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PPCI_ANDISDOT = 0x74000000,
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PPCI_OR = 0x7c000378,
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PPCI_NOR = 0x7c0000f8,
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PPCI_ORI = 0x60000000,
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PPCI_ORIS = 0x64000000,
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PPCI_XOR = 0x7c000278,
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PPCI_EQV = 0x7c000238,
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PPCI_XORI = 0x68000000,
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PPCI_XORIS = 0x6c000000,
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PPCI_CMPW = 0x7c000000,
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PPCI_CMPLW = 0x7c000040,
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PPCI_CMPWI = 0x2c000000,
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PPCI_CMPLWI = 0x28000000,
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PPCI_MULLW = 0x7c0001d6,
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PPCI_MULLI = 0x1c000000,
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PPCI_MULLWO = 0x7c0005d6,
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PPCI_EXTSB = 0x7c000774,
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PPCI_EXTSH = 0x7c000734,
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PPCI_SLW = 0x7c000030,
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PPCI_SRW = 0x7c000430,
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PPCI_SRAW = 0x7c000630,
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PPCI_SRAWI = 0x7c000670,
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PPCI_RLWNM = 0x5c000000,
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PPCI_RLWINM = 0x54000000,
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PPCI_RLWIMI = 0x50000000,
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PPCI_B = 0x48000000,
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PPCI_BL = 0x48000001,
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PPCI_BC = 0x40800000,
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PPCI_BCL = 0x40800001,
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PPCI_BCTR = 0x4e800420,
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PPCI_BCTRL = 0x4e800421,
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PPCI_CRANDC = 0x4c000102,
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PPCI_CRXOR = 0x4c000182,
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PPCI_CRAND = 0x4c000202,
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PPCI_CREQV = 0x4c000242,
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PPCI_CRORC = 0x4c000342,
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PPCI_CROR = 0x4c000382,
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PPCI_MFLR = 0x7c0802a6,
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PPCI_MTCTR = 0x7c0903a6,
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PPCI_MCRXR = 0x7c000400,
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/* Load/store instructions. */
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PPCI_LWZ = 0x80000000,
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PPCI_LBZ = 0x88000000,
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PPCI_STW = 0x90000000,
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PPCI_STB = 0x98000000,
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PPCI_LHZ = 0xa0000000,
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PPCI_LHA = 0xa8000000,
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PPCI_STH = 0xb0000000,
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PPCI_STWU = 0x94000000,
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PPCI_LFS = 0xc0000000,
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PPCI_LFD = 0xc8000000,
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PPCI_STFS = 0xd0000000,
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PPCI_STFD = 0xd8000000,
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PPCI_LWZX = 0x7c00002e,
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PPCI_LBZX = 0x7c0000ae,
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PPCI_STWX = 0x7c00012e,
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PPCI_STBX = 0x7c0001ae,
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PPCI_LHZX = 0x7c00022e,
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PPCI_LHAX = 0x7c0002ae,
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PPCI_STHX = 0x7c00032e,
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PPCI_LWBRX = 0x7c00042c,
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PPCI_STWBRX = 0x7c00052c,
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PPCI_LFSX = 0x7c00042e,
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PPCI_LFDX = 0x7c0004ae,
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PPCI_STFSX = 0x7c00052e,
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PPCI_STFDX = 0x7c0005ae,
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/* FP instructions. */
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PPCI_FMR = 0xfc000090,
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PPCI_FNEG = 0xfc000050,
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PPCI_FABS = 0xfc000210,
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PPCI_FRSP = 0xfc000018,
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PPCI_FCTIWZ = 0xfc00001e,
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PPCI_FADD = 0xfc00002a,
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PPCI_FSUB = 0xfc000028,
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PPCI_FMUL = 0xfc000032,
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PPCI_FDIV = 0xfc000024,
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PPCI_FSQRT = 0xfc00002c,
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PPCI_FMADD = 0xfc00003a,
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PPCI_FMSUB = 0xfc000038,
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PPCI_FNMSUB = 0xfc00003c,
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PPCI_FCMPU = 0xfc000000,
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PPCI_FSEL = 0xfc00002e,
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} PPCIns;
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typedef enum PPCCC {
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CC_GE, CC_LE, CC_NE, CC_NS, CC_LT, CC_GT, CC_EQ, CC_SO
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} PPCCC;
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#endif
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