mirror of https://github.com/axmolengine/axmol.git
424 lines
9.4 KiB
C
424 lines
9.4 KiB
C
// SPDX-License-Identifier: Apache-2.0
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// ----------------------------------------------------------------------------
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// Copyright 2020-2021 Arm Limited
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//
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// Licensed under the Apache License, Version 2.0 (the "License"); you may not
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// use this file except in compliance with the License. You may obtain a copy
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// of the License at:
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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// License for the specific language governing permissions and limitations
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// under the License.
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// ----------------------------------------------------------------------------
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/**
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* @brief Generic 4x32-bit vector functions.
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*
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* This module implements generic 4-wide vector functions that are valid for
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* all instruction sets, typically implemented using lower level 4-wide
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* operations that are ISA-specific.
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*/
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#ifndef ASTC_VECMATHLIB_COMMON_4_H_INCLUDED
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#define ASTC_VECMATHLIB_COMMON_4_H_INCLUDED
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#ifndef ASTCENC_SIMD_INLINE
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#error "Include astcenc_vecmathlib.h, do not include directly"
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#endif
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#include <cstdio>
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// ============================================================================
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// vmask4 operators and functions
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// ============================================================================
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/**
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* @brief True if any lanes are enabled, false otherwise.
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*/
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ASTCENC_SIMD_INLINE bool any(vmask4 a)
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{
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return mask(a) != 0;
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}
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/**
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* @brief True if all lanes are enabled, false otherwise.
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*/
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ASTCENC_SIMD_INLINE bool all(vmask4 a)
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{
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return mask(a) == 0xF;
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}
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// ============================================================================
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// vint4 operators and functions
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// ============================================================================
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/**
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* @brief Overload: vector by scalar addition.
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*/
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ASTCENC_SIMD_INLINE vint4 operator+(vint4 a, int b)
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{
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return a + vint4(b);
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}
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/**
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* @brief Overload: vector by vector incremental addition.
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*/
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ASTCENC_SIMD_INLINE vint4& operator+=(vint4& a, const vint4& b)
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{
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a = a + b;
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return a;
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}
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/**
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* @brief Overload: vector by scalar subtraction.
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*/
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ASTCENC_SIMD_INLINE vint4 operator-(vint4 a, int b)
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{
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return a - vint4(b);
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}
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/**
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* @brief Overload: vector by scalar multiplication.
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*/
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ASTCENC_SIMD_INLINE vint4 operator*(vint4 a, int b)
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{
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return a * vint4(b);
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}
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/**
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* @brief Overload: vector by scalar bitwise or.
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*/
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ASTCENC_SIMD_INLINE vint4 operator|(vint4 a, int b)
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{
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return a | vint4(b);
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}
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/**
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* @brief Overload: vector by scalar bitwise and.
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*/
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ASTCENC_SIMD_INLINE vint4 operator&(vint4 a, int b)
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{
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return a & vint4(b);
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}
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/**
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* @brief Overload: vector by scalar bitwise xor.
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*/
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ASTCENC_SIMD_INLINE vint4 operator^(vint4 a, int b)
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{
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return a ^ vint4(b);
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}
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/**
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* @brief Return the clamped value between min and max.
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*/
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ASTCENC_SIMD_INLINE vint4 clamp(int minv, int maxv, vint4 a)
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{
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return min(max(a, vint4(minv)), vint4(maxv));
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}
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/**
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* @brief Return the horizontal sum of RGB vector lanes as a scalar.
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*/
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ASTCENC_SIMD_INLINE int hadd_rgb_s(vint4 a)
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{
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return a.lane<0>() + a.lane<1>() + a.lane<2>();
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}
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// ============================================================================
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// vfloat4 operators and functions
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// ============================================================================
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/**
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* @brief Overload: vector by vector incremental addition.
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*/
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ASTCENC_SIMD_INLINE vfloat4& operator+=(vfloat4& a, const vfloat4& b)
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{
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a = a + b;
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return a;
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}
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/**
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* @brief Overload: vector by scalar addition.
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*/
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ASTCENC_SIMD_INLINE vfloat4 operator+(vfloat4 a, float b)
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{
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return a + vfloat4(b);
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}
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/**
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* @brief Overload: vector by scalar subtraction.
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*/
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ASTCENC_SIMD_INLINE vfloat4 operator-(vfloat4 a, float b)
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{
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return a - vfloat4(b);
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}
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/**
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* @brief Overload: vector by scalar multiplication.
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*/
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ASTCENC_SIMD_INLINE vfloat4 operator*(vfloat4 a, float b)
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{
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return a * vfloat4(b);
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}
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/**
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* @brief Overload: scalar by vector multiplication.
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*/
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ASTCENC_SIMD_INLINE vfloat4 operator*(float a, vfloat4 b)
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{
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return vfloat4(a) * b;
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}
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/**
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* @brief Overload: vector by scalar division.
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*/
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ASTCENC_SIMD_INLINE vfloat4 operator/(vfloat4 a, float b)
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{
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return a / vfloat4(b);
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}
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/**
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* @brief Overload: scalar by vector division.
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*/
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ASTCENC_SIMD_INLINE vfloat4 operator/(float a, vfloat4 b)
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{
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return vfloat4(a) / b;
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}
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/**
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* @brief Return the min vector of a vector and a scalar.
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*
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* If either lane value is NaN, @c b will be returned for that lane.
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*/
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ASTCENC_SIMD_INLINE vfloat4 min(vfloat4 a, float b)
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{
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return min(a, vfloat4(b));
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}
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/**
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* @brief Return the max vector of a vector and a scalar.
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*
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* If either lane value is NaN, @c b will be returned for that lane.
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*/
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ASTCENC_SIMD_INLINE vfloat4 max(vfloat4 a, float b)
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{
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return max(a, vfloat4(b));
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}
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/**
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* @brief Return the clamped value between min and max.
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*
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* It is assumed that neither @c min nor @c max are NaN values. If @c a is NaN
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* then @c min will be returned for that lane.
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*/
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ASTCENC_SIMD_INLINE vfloat4 clamp(float minv, float maxv, vfloat4 a)
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{
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// Do not reorder - second operand will return if either is NaN
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return min(max(a, minv), maxv);
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}
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/**
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* @brief Return the clamped value between 0.0f and max.
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*
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* It is assumed that @c max is not a NaN value. If @c a is NaN then zero will
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* be returned for that lane.
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*/
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ASTCENC_SIMD_INLINE vfloat4 clampz(float maxv, vfloat4 a)
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{
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// Do not reorder - second operand will return if either is NaN
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return min(max(a, vfloat4::zero()), maxv);
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}
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/**
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* @brief Return the clamped value between 0.0f and 1.0f.
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*
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* If @c a is NaN then zero will be returned for that lane.
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*/
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ASTCENC_SIMD_INLINE vfloat4 clampzo(vfloat4 a)
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{
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// Do not reorder - second operand will return if either is NaN
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return min(max(a, vfloat4::zero()), 1.0f);
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}
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/**
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* @brief Return the horizontal minimum of a vector.
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*/
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ASTCENC_SIMD_INLINE float hmin_s(vfloat4 a)
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{
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return hmin(a).lane<0>();
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}
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/**
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* @brief Return the horizontal min of RGB vector lanes as a scalar.
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*/
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ASTCENC_SIMD_INLINE float hmin_rgb_s(vfloat4 a)
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{
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a.set_lane<3>(a.lane<0>());
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return hmin_s(a);
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}
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/**
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* @brief Return the horizontal maximum of a vector.
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*/
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ASTCENC_SIMD_INLINE float hmax_s(vfloat4 a)
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{
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return hmax(a).lane<0>();
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}
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/**
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* @brief Accumulate lane-wise sums for a vector.
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*/
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ASTCENC_SIMD_INLINE void haccumulate(vfloat4& accum, vfloat4 a)
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{
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accum = accum + a;
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}
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/**
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* @brief Accumulate lane-wise sums for a masked vector.
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*/
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ASTCENC_SIMD_INLINE void haccumulate(vfloat4& accum, vfloat4 a, vmask4 m)
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{
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a = select(vfloat4::zero(), a, m);
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haccumulate(accum, a);
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}
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/**
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* @brief Return the horizontal sum of RGB vector lanes as a scalar.
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*/
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ASTCENC_SIMD_INLINE float hadd_rgb_s(vfloat4 a)
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{
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return a.lane<0>() + a.lane<1>() + a.lane<2>();
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}
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#if !defined(ASTCENC_USE_NATIVE_DOT_PRODUCT)
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/**
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* @brief Return the dot product for the full 4 lanes, returning scalar.
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*/
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ASTCENC_SIMD_INLINE float dot_s(vfloat4 a, vfloat4 b)
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{
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vfloat4 m = a * b;
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return hadd_s(m);
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}
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/**
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* @brief Return the dot product for the full 4 lanes, returning vector.
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*/
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ASTCENC_SIMD_INLINE vfloat4 dot(vfloat4 a, vfloat4 b)
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{
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vfloat4 m = a * b;
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return vfloat4(hadd_s(m));
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}
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/**
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* @brief Return the dot product for the bottom 3 lanes, returning scalar.
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*/
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ASTCENC_SIMD_INLINE float dot3_s(vfloat4 a, vfloat4 b)
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{
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vfloat4 m = a * b;
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return hadd_rgb_s(m);
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}
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/**
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* @brief Return the dot product for the bottom 3 lanes, returning vector.
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*/
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ASTCENC_SIMD_INLINE vfloat4 dot3(vfloat4 a, vfloat4 b)
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{
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vfloat4 m = a * b;
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float d3 = hadd_rgb_s(m);
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return vfloat4(d3, d3, d3, 0.0f);
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}
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#endif
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#if !defined(ASTCENC_USE_NATIVE_POPCOUNT)
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/**
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* @brief Population bit count.
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*
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* @param v The value to population count.
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*
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* @return The number of 1 bits.
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*/
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static inline int popcount(uint64_t v)
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{
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uint64_t mask1 = 0x5555555555555555ULL;
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uint64_t mask2 = 0x3333333333333333ULL;
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uint64_t mask3 = 0x0F0F0F0F0F0F0F0FULL;
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v -= (v >> 1) & mask1;
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v = (v & mask2) + ((v >> 2) & mask2);
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v += v >> 4;
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v &= mask3;
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v *= 0x0101010101010101ULL;
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v >>= 56;
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return static_cast<int>(v);
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}
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#endif
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/**
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* @brief Apply signed bit transfer.
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*
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* @param input0 The first encoded endpoint.
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* @param input1 The second encoded endpoint.
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*/
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static ASTCENC_SIMD_INLINE void bit_transfer_signed(
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vint4& input0,
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vint4& input1
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) {
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input1 = lsr<1>(input1) | (input0 & 0x80);
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input0 = lsr<1>(input0) & 0x3F;
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vmask4 mask = (input0 & 0x20) != vint4::zero();
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input0 = select(input0, input0 - 0x40, mask);
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}
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/**
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* @brief Debug function to print a vector of ints.
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*/
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ASTCENC_SIMD_INLINE void print(vint4 a)
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{
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alignas(16) int v[4];
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storea(a, v);
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printf("v4_i32:\n %8d %8d %8d %8d\n",
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v[0], v[1], v[2], v[3]);
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}
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/**
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* @brief Debug function to print a vector of ints.
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*/
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ASTCENC_SIMD_INLINE void printx(vint4 a)
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{
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alignas(16) int v[4];
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storea(a, v);
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printf("v4_i32:\n %08x %08x %08x %08x\n",
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v[0], v[1], v[2], v[3]);
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}
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/**
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* @brief Debug function to print a vector of floats.
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*/
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ASTCENC_SIMD_INLINE void print(vfloat4 a)
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{
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alignas(16) float v[4];
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storea(a, v);
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printf("v4_f32:\n %0.4f %0.4f %0.4f %0.4f\n",
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static_cast<double>(v[0]), static_cast<double>(v[1]),
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static_cast<double>(v[2]), static_cast<double>(v[3]));
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}
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/**
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* @brief Debug function to print a vector of masks.
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*/
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ASTCENC_SIMD_INLINE void print(vmask4 a)
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{
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print(select(vint4(0), vint4(1), a));
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}
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#endif // #ifndef ASTC_VECMATHLIB_COMMON_4_H_INCLUDED
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